The present invention relates to an image input/output control system which effectively controls, for example, an image input apparatus such as a scanner and an image output apparatus such as a printer.
There has conventionally been put to practical use an image processing system called a composite appliance such as a copying machine or a facsimile which is equipped with a combination of an image input apparatus such as a scanner and an image output apparatus such as a printer as well as a computer system which is equipped with an image input apparatus and an image output apparatus as separate component units. When the image processing system is incapable of operating the image input apparatus and the image output apparatus in synchronization with each other, a composite function such as a copying function is realized by outputting image data which is taken from the image input apparatus once into a memory to the image output apparatus. When the image processing system is capable of operating the image input apparatus and the image output apparatus in synchronization with each other, the composite function such as the copying function is realized by disposing a passage which transfers an image signal from the image input apparatus directly to the image output apparatus.
The conventional image processing system adopts an optimum circuit configuration dependently on functions of the image input apparatus and the image output apparatus as described above.
Furthermore, an interface circuit which connects an image input apparatus to an image output apparatus is optimized according to specifications for the image input apparatus and the image output apparatus and specifications for a bus to be connected.
When a configuration of the interface circuit is optimized to functions of the image input apparatus and the image output apparatus as described above, the configuration of the interface circuit must be modified each time the image input apparatus and the image output apparatus are modified. Accordingly, the conventional image processing system poses a first problem that it does not permit free selection for use of various kinds of image input apparatuses and image output apparatuses.
Furthermore, the conventional image processing system poses a second problem that it fixes uses of hardware resources such as memories and buses, thereby making it impossible to optimize the hardware resources dependently on various operating modes.
When the copying function is realized by outputting a image signal which is taken from the image input apparatus once into the memory to the image output apparatus, the conventional image processing system poses a third problem that it requires reserving a memory area even during a copying operation.
When the copying function is realized by disposing a passage which connects the image input apparatus directly to the image output apparatus in addition to passages which connect the image input apparatus and the image output apparatus to the memory, the conventional image processing system poses a fourth problem that a hardware configuration is complicated, thereby constituting a cause to enhance a cost.
When the configuration of the interface circuit is optimized to the specifications for the image input apparatus and the image output apparatus as well as the specifications for the bus to be connected, the conventional image processing system poses a fifth problem that it requires modification of the configuration of the interface circuit when the specifications for the image input apparatus and the image output apparatus are changed, when the image input apparatus or the image output apparatus is exchanged or when the specifications for the bus are changed.
A primary object of the present invention which has been achieved in view of the conventional example described above is to provide a control system for composite appliances which prepares a plurality of passages as image signal passages corresponding to functions of image input apparatuses and image output apparatuses, and permits selecting an optimum passages out of the image signal passages, thereby requiring no modification of a circuit configuration even when an image input apparatuses and an image output apparatus are changed and permitting freely selecting for use of a various kinds of image input apparatus and image output apparatus.
A secondary object of the present invention is to provide a control system for composite appliances which permits using hardware resources such as memories and buses dependently on various operating modes such as a mode to connect an image input apparatus directly to an image output apparatus, a mode to connect the image input apparatus to the image output apparatus by way of a FIFO and a mode to store image data read from the image input apparatus once into a memory and then output the image data to the image output apparatus.
A tertiary object of the present invention is to provide a control system for composite appliances which buffers difference in data rate between an image input apparatus and an image output apparatus with a FIFO when a copying function is realized by outputting a image signal taken from an image input apparatus to an image output apparatus, thereby eliminating the necessity to reserve a memory area for copying.
A quaternary object of the present invention is to provide a control system for composite appliances which permits simplifying a hardware configuration regardless of kinds of image input apparatuses and image output apparatuses by preparing a configuration for direct connection of controllers of the image input apparatus and the image output apparatus even when a copying function is realized by providing a passage which connect the image input apparatus directly to the image output apparatus in addition to passages which connect the image input apparatus and the image output apparatus to the memory.
A quaternary object of the present invention is to provide a control system for composite appliances which uses a common interface circuit for a bus regardless of specifications for an image input apparatus and an image output apparatus, and comprises a configuration which converts input/output signals from the image input apparatus and the image output apparatus into input/output signals for a bus interface, thereby eliminating a necessity to change a configuration of the interface circuit.
In order to accomplish the objects described above, an image input/output control system as an aspect of the present invention comprises:
receiving means which receives a image signal from image input means;
transmitting means which sends out the image signal to image output means;
connecting means which connects the receiving means to the transmitting means by way of a plurality of passages; and
transferring means which selects one of the plurality of passages and transfers the image signal from the receiving means to the transmitting means by way of the selected passage.
It is more preferable that the image input/output control system further comprises memory means which is capable of storing the image signal and a bus which connects the memory means, the receiving means and the transmitting means, that the connecting means connects the receiving means to the transmitting means through at least three passages: a first passage for direct connection, a second passage by way of the bus, and a third passage by way of the bus and the memory means; and that the transferring means transfers the image signal through any one of the three passages.
It is more preferable to configure the image input/output control system so that the transferring means selects the first passage when an input timing of the image input means is coincident with an output timing of the image output means in vertical synchronous signals, horizontal synchronous signals and video clock signals, the second passage when the input timing of the image input means is coincident with the output timing of the image output means only in the horizontal synchronous signals or the third passage when the input timing of the image input means is coincident with the output timing of the image output means in no signals.
It is more preferable to configure the image input/output control system so that the transferring means selects the third passage when a image signal input from the image input means is to be processed.
It is more preferable to configure the image input/output control system so that the receiving means comprises a FIFO buffer which receives the image signal input from the image input means and the transmitting means comprises a FIFO buffer which transmits the image signal to the image output means.
It is more preferable to configure the image input/output control system so that the receiving means and the transmitting means each have two stages of FIFO buffers.
It is more preferable to configure the image input/output control system so that the bus comprises a plurality of buses which are different from one another, the second passage passes by way of any one of the buses different from one another and the transferring means selects a passage which passes by way of a bus having a fastest speed out of the plurality of buses as a passage to transfer the image signal.
It is more preferable to configure the image input/output control system so that the receiving means comprises first conversion means which converts a type of an image represented by the image signal from the image input means.
It is more preferable to configure the image input/output control system so that the transmitting means comprises second conversion means which converts a type of an image represented by the image signal in order to transmit it to the image output means.
It is more preferable to configure the image input/output control system so that the receiving means and transmitting means transmitting the image signal using the buses as bus masters.
Furthermore, an image input/output control system as another aspect of the present invention comprises:
a plurality of buses;
an input controller which inputs a image signal from image signal input means;
a first bus interface which connects the input controller to at least one of the plurality of buses;
an output controller which outputs the image signal to image signal output means;
a second bus interface which connects the output controller to at least one of the plurality of buses;
a memory to which access can be made from the plurality of buses respectively; and
a controller bus which connects the input controller to the output controller,
wherein the image input/output control system transfers a image signal from the image signal input means to the image signal output means in any one of a firsts mode in which the image signal is transferred from the input controller directly to the output controller, a second mode in which the image signal is transferred from the first bus interface to the second bus interface and a third mode in which the image signal is transferred from the first bus interface to the memory, from which it is transferred to the second bus interface.
It is more preferable that the image input/output control system selects one of the three transfer modes dependently on functions of the image signal input means and the image signal output means.
It is more preferable that the image input/output control system selects one of the three transfer modes dependently on whether or not the image signal is to be processed.
It is more preferable that the image input/output control system selects one of the three transfer modes dependently on conditions of use of the memory and buses.
Alternately, the image input/output control system in still another aspect of the present invention comprises:
an input controller which inputs a image signal;
a first bus interface which connects the input controller to a bus;
an output controller which outputs the image signal; and
a second bus interface which connects the output controller to the bus,
wherein the input controller comprises a FIFO buffer which absorbs a difference in transfer timing from an input source of the image signal, the first bus interface comprises a FIFO buffer which absorbs a difference in transfer timing from the bus, the second bus interface comprises a FIFO buffer which absorbs a difference in transfer timing from the bus and the output controller comprises a FIFO buffer which absorbs a difference in transfer timing from a transfer destination of an output image signal.
Alternately, the image input/output control system in still another aspect of the present invention comprises:
an input controller which inputs a image signal in compliance with an input image signal format;
a first bus interface which connects the input controller to a bus;
an output controller which outputs the image signal in compliance with an output image signal format; and
a second bus interface which connects the output controller to the bus,
wherein the input controller comprises first conversion means which converts the input image signal format into an image format for the first bus interface and a FIFO buffer which absorbs a difference in transfer timing between the input image signal and the first bus interface, wherein the first bus interface comprises a FIFO buffer which absorbs a difference in transfer timing between the first bus interface and the bus,
wherein the second bus interface comprises a FIFO buffer which absorbs a difference in transfer timing between the bus and the second bus interface, and
wherein the output controller comprises second conversion means which converts an image format for the second bus interface into an output image signal format and a FIFO buffer which absorbs a difference in transfer timing between the second bus interface and an output image signal.
It is more preferable to configure the image input/output control system so that the input image signal format and the output image signal format include formats representing binary image data, many-valued image data, color image data and compressed image data.
It is more preferable to configure the image input/output control system so that the input image signal format is a format in which image signals corresponding to at least two pixels are input in parallel and the output image signal format is a format in which image signals corresponding to at least two pixels are output in parallel.
Furthermore, an image input/output control system in further another aspect of the present invention comprises:
an input controller which inputs a image signal;
a first bus interface which connects the input controller to a bus;
an output controller which outputs the image signal; and
a second bus interface which connects the output controller to the bus,
wherein the input controller comprises a FIFO buffer which absorbs a difference in transfer timing between the input image signal and the first bus interface,
wherein the first bus interface comprises a FIFO buffer which absorbs a difference in transfer timing between the first bus interface and the bus, and first DMA control means which controls DMA transfer to the bus,
wherein the second bus interface comprises a FIFO buffer which absorbs a difference in transfer timing between the bus and the second bus interface, and second DMA control means which controls DMA transfer from the bus, and
wherein the output controller comprises a FIFO buffer which absorbs a difference in transfer timing between the second bus interface and the output image signal,
whereby the image signal is transferred from the first bus interface to the second bus interface by the first and second DMA control means.
It is more preferable to configure the image input/output control system so that the DMA transfer from the first bus interface to the second bus interface can be controlled by either of the first DMA control means and the second DMA control means.
It is more preferable to configure the image input/output control system so that the DMA transfer from the first bus interface to the second bus interface is controlled by the first DMA control means or the second DMA control means whichever has no margin in the image signal transfer timing.
It is more preferable to configure the image input/output control system so that the first bus interface and the second bus interface are connected to a plurality of buses, and the DMA transfer is carried out using a bus which is used at a lowest frequency out of the plurality of buses.
It is more preferable that the image input/output control system is configured as a semiconductor device formed on a single semiconductor substrate.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.